Why ARM opened up its instruction set and what it means for IoT

Chip design firm ARM, which developed the underlying architecture used in almost every cell phone processor in the world, has just opened up that architecture further for customization. In a huge move for the 29-year-old company, it said it would let partners customize the ARM instruction set architecture (ISA) to help improve the performance and efficiency of the partners’ end devices.

ARM’s instruction set is the core intellectual property, and the source of its revenue from chip firms such as Qualcomm, NXP and even computing companies such as Apple and Google, which license the architecture for their own chips. An instruction set (ISA) is the lowest level of silicon architecture, telling a computer programmer how to handle data flow and state on a chip. ARM’s has been optimized for performing tasks with greater energy efficiency. This has helped it gain ground in cell phones and as the underlying chip architecture for the internet of things.

The permission to tweak the ARM instruction set acknowledges the changing reality of chip world, which is adapting to two big shifts; the number of devices that need chips is expanding and the types of jobs they do are fragmented into a huge number of workloads. These workloads might range from temperature easing all the way up to running a machine learning model for computer vision.

The entire chip industry is reacting to these trends. Intel, the creator of its own x86 architecture,  is embracing other instruction sets and programmable chips. Qualcomm, NXP and other traditional ARM customers are consolidating. And companies such as Nvidia and Western Digital that have designed their own ISAs for dedicated internal processors are turning to an open-source instruction set called RISC-V that gives them the ability to customize chips to meet highly individual needs.

Broadly, the core of this trend is a demand for more processing power with a greater emphasis on energy efficiency. Machine learning requires a lot of computing power while many of the new homes for chips are battery-powered. To eke out those efficiency gains, chip firms have turned to a variety of design tweaks such as assigning a co-processor to perform a dedicated function such as motion-detection or wake-word detection. For example, Apple uses a co-processor for motion detection in the Apple Watch, allowing it to detect steps without needing to turn to the relatively power-hungry main processor.

Another design technique is to perform processing in-memory to make calculations faster and give a performance boost. This is becoming more common in chips that are designed to perform machine learning tasks. But in-memory processing requires a specially designed chip that needs customized firmware and can only run certain software. Building that software takes resources and generally limits the types of applications those types of devices can run.

ARM’s decision to open up its instruction set will allow companies to take advantage of the huge network of software support for ARM while also embedding dedicated math into the instruction set for their specific use case. Alessandro Pi0vaccari, the CTO at Silicon Labs, says this level of software support is important, and that Silicon Labs has several ways it can take advantage of the customization. 

Joe Cirello, Technical Fellow, Chief MCU Core Platform and Security Architect at NXP agrees. “Often times a general-purpose ISA can be optimized for better performance and better power and in general, but there’s an emerging set of applications that are relatively new and may have different requirements than some of the more traditional MCU applications of the past,” says Cirello. He says especially IoT nodes and edge computing devices need more performance for security or machine learning that could benefit from a customized ISA.

It means NXP could develop a chip that could have a dedicated function for detecting a wake word as part of the processor, but also the ability to run popular apps. Customers have been pushing ARM to let them customize the ISA for a few years, and under pressure from the changing environment and the threat of RISC-V, it is.

ARM doesn’t talk about RISC-V, but it’s clearly a factor in many of its recent decisions. The RISC-V instruction set was developed by researchers at Berkeley to provide an open-source architecture for low-power computing. RISC-V was exciting for computing nerds, but it didn’t really become a threat until a company called SiFive started building out the support and tools that a company would need to use in order to design a RISC-V processor.

Until that point, a team of dedicated chip designers could build a RISC-V processor and another team of firmware and compiler experts could build supporting software to make things run on a RISC-V processor, but that type of support only exists at a few companies. Additionally, back in 2012 and even 2015 when SiFive was started, the number of places where the combination of effort and design made sense was limited. Nvidia used RISC-V to build a chip that managed the many GPU cores on it gaming processors, but it already had a dedicated hardware and software team familiar with silicon design.

But the market was changing. In 2016 I met with a company called Greenwaves that had a few chip designers building a new chip for IoT that was taking the RISC-V ISA and adapting it. They chose that architecture because it was open-source and they could save “a few million” on ARM licensing costs, according to the firm’s CEO. Because the chip would become part of a subsystem instead of a general purpose device that would need to run popular apps, the lack of higher-level software didn’t matter as much.

But moves like Nvidia’s and Greenwaves were exposing a weakness in ARM’s business. It was becoming apparent that the company had to do something to address the demands of its largest customers and continue to appeal to startups trying to build the next-generation of silicon that would go in a variety of new devices.

Roughly two months ago ARM said it would offer free licenses to startups and researchers trying to build new types of silicon. The idea was to let companies play with putting ARM-based processors into new designs that could be optimized for power management or slight tweaks on processing power. Once a design reached production stage, the company would pay the full licensing fees, but it gave companies room to experiment without such high up-front costs.

And today with the opening up of the ISA, ARM is giving customers large and small a lot more flexibility. 

There are limits. ARM has opened up the instruction set on the M-33 processors, a microcontroller that goes into smaller, battery-powered devices. ARM also has a line of A-class processors destined for severs, cell phone base stations and cell phone processors. The A-class designs are not getting the freedom afforded an open instruction set.

Surprisingly, ARM will not charge more for the ability to tweak the ISA. Kevin Krewell, an analyst with Trias Research says the decision to open up further is a necessary one and a sign that the purchase of ARM back in 2016 by Softbank is slowly changing the culture at the firm. Given the demands of today’s computing world, those changes are necessary. It’s good to see ARM make them.